1. Field of the Invention
The present invention relates to the structure of a MOSFET (metal-oxide semiconductor field-effect transistor) for an open-drain circuit, and to a semiconductor integrated circuit device employing such a MOSFET. More particularly, the present invention relates to an improvement on the withstand voltage of a MOSFET for an open-drain circuit.
2. Description of the Prior Art
Conventionally, an open-drain output circuit as shown in FIG. 4 has been widely used as the output circuit of a semiconductor integrated circuit device. An input terminal 101 is connected to the gate of an N-channel MOSFET (hereinafter referred to as the “NMOS”) for an open-drain circuit. The drain of the NMOS 102 is connected to an output terminal 103, and the source of the NMOS 102 is connected to ground. To the input terminal 101 of the output circuit is fed, for example, a signal output from a CMOS (complementary metal-oxide semiconductor) logic circuit provided in the semiconductor integrated circuit device.
In the open-drain output circuit shown in FIG. 4, when a high-level signal is fed to the input terminal 101, the NMOS 102 turns on, turning the output terminal 103 to a low level. On the other hand, when a low-level signal is fed to the input terminal 101, the NMOS 102 turns off, bringing the output terminal 103 into an electrically floating state (a high-impedance state). At the drain, a parasitic diode Di is formed.
In a non-operating state, (i.e., when the NMOS 102 is off), an abnormal static electric charge may be applied to the output terminal 103 for some reason or other. In the open-drain output circuit shown in FIG. 4, while a negative static electric charge is readily discharged by way of the parasitic diode Di, there is no route by way of which to discharge a positive static electric charge. As a result, when a static electric charge higher than the gate withstand voltage or drain-source withstand voltage of the NMOS 102 is applied to the output terminal 103, the NMOS 102 is liable to be destroyed between its drain and gate or between its drain and source.
FIG. 5 is a sectional view schematically showing the conventional NMOS structure used as the NMOS 102. The conventional NMOS structure is formed in a device-forming region between field oxide films (LOCOS) 2a and 2b on a P-type semiconductor substrate 1 such as a silicon substrate.
On the P-type semiconductor substrate 1, high-concentration N-type impurity diffusion regions (source regions 3a and 3b and a drain region 4) are formed. Between the field oxide films 2a and 2b and the source regions 3a and 3b, high-concentration P-type impurity diffusion regions 5a and 5b are formed. Between the source regions 3a and 3b and the drain region 4, contiguous with the drain region 4, low-concentration N-type impurity diffusion regions 6a and 6b are formed, with a LOCOS 7a formed on top of the low-concentration N-type impurity diffusion region 6a and a LOCOS 7b formed on the low-concentration N-type impurity diffusion region 6b. On top of the channel regions between the source regions 3a and 3b and the low-concentration N-type impurity diffusion regions 6a and 6b, gate insulating films 8a and 8b are formed, with polysilicon films formed as gate electrodes 9a and 9b on top of the gate insulating films 8a and 8b. The drain region 4 is connected to a drain lead electrode D. The gate electrodes 9a and 9b are connected to a gate lead electrode G. The source regions 3a and 3b are connected to a source lead electrode S. The high-concentration P-type impurity diffusion regions 5a and 5b are connected to a backgate lead electrode BG. In the low-concentration regions (N− and P-sub), parasitic resistance components R1′ and R2′ are formed respectively. Parasitic resistance components are formed also in the high-concentration regions constituting the drain and source, but these are not illustrated, because their resistances are low as compared with that of the parasitic resistance component R1′.
FIG. 6 shows the equivalent circuit of a conventionally structured MOSFET in its state in which the source lead electrode S and the backgate lead electrode BG are kept at an equal potential. In FIG. 6, such circuit elements as are found in FIG. 5 are identified with the same reference symbols. The drain lead electrode D is connected through the parasitic resistor R1′ to the drain of the MOSFET 16 and to the collector of an NPN-type parasitic transistor Q1. The base of the parasitic transistor Q1 is connected to one end of the parasitic resistor R2′. The source of the MOSFET 16, the emitter of the parasitic transistor Q1, and the other end of the parasitic resistor R2′ are connected to the source lead electrode S and to the backgate lead electrode BG.
In the conventionally structured NMOS shown in FIG. 5, when a positive static electric charge is applied to the drain lead electrode D, the NMOS 16 and the parasitic transistor Q1 both remain off (see FIG. 6), and therefore there is no route by way of which to discharge the static electric charge. This makes the static withstand voltage of the conventionally structured NMOS rather low, specifically as low as +300 V to +600 V as measured under the HBM (human body model) condition, or +150 V to +250 V as measured under the MM (machine model) condition.
Incidentally, Japanese Patent Registered No. 3204168 discloses an invention relating to a semiconductor integrated circuit that can alleviate the lowering of the on-state withstand voltage of a transistor. However, this publication discloses nothing about the static withstand voltage of a MOSFET for an open-drain circuit.